MC100E142 |
RFQ for MC100E142 Required Field |
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| Technical/Catalog Information | MC100E142FNG |
| Vendor | ON Semiconductor |
| Category | Integrated Circuits (ICs) |
| Logic Type | Shift Register |
| Function | Universal |
| Number of Elements | 1 - Single |
| Number of Bits per Element | 9 |
| Output Type | Standard |
| Voltage - Supply | 4.2 V ~ 5.7 V |
| Mounting Type | Surface Mount |
| Package / Case | 28-PLCC |
| Packaging | Tube |
| Operating Temperature | 0°C ~ 85°C |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | MC100E142FNG MC100E142FNG MC100E142FNGOS ND MC100E142FNGOSND MC100E142FNGOS |
| Product | Manufacturers | Pack | D/C |
| MC100E142 | - | PLCC28 | 07/08+ |
The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.
Features |
| `700MHz Min. Shift Frequency`9-Bit for Byte-Parity Applications` Asynchronous Master Reset` Dual Clocks` Extended 100E VEE Range of 4.2V to 5.46V` 75k Input Pulldown ResistorsThe SEL (Select) input pin is used to switch between the two modes of operation - SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the resisters to zero. |
